82801DB Datasheet, PDF (267/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LAN Controller Registers (B1:D8:F0)
Table 7-5. Self-Test Results Format
Bit
Description
31:13 Reserved
General Self-Test Result — R/W (special).
12 0 = Pass
1 = Fail
11:6 Reserved
Diagnose Result — R/W (special). This bit provides the result of an internal diagnostic test of the
Serial Subsystem.
5
0 = Pass
1 = Fail
4 Reserved
Register Result — R/W (special). This bit provides the result of a test of the internal Parallel
Subsystem registers.
3
0 = Pass
1 = Fail
ROM Content Result — R/W (special). This bit provides the result of a test of the internal
microcode ROM.
2
0 = Pass
1 = Fail
1:0 Reserved
7.2.5
EEPROM Control Register
Offset Address: 0Eh
Default Value: 00h
Attribute:
Size:
RO, R/W, WO
8 bits
The EEPROM Control Register is a 16-bit field that enables a read from and a write to the external
EEPROM.
Bit
Description
7:4 Reserved
EEPROM Serial Data Out (EEDO)— RO. Note that this bit represents "Data Out" from the
3 perspective of the EEPROM device. This bit contains the value read from the EEPROM when
performing read operations.
EEPROM Serial Data In (EEDI)— WO. Note that this bit represents "Data In" from the perspective
2 of the EEPROM device. The value of this bit is written to the EEPROM when performing write
operations.
EEPROM Chip Select (EECS)— R/W.
1
0 = Drives the Intel^® ICH4’s EE_CS signal low, to disable the EEPROM. this bit must be set to 0 for
a minimum of 1 µs between consecutive instruction cycles.
1 = Drives the ICH4’s EE_CS signal high, to enable the EEPROM.
EEPROM Serial Clock (EESK)— R/W. Toggling this bit, clocks data into or out of the EEPROM.
Software must ensure that this bit is toggled at a rate that meets the EEPROM component’s
0
minimum clock frequency specification.
0 = Drives the ICH4’s EE_SHCLK signal low.
1 = Drives the ICH4’s EE_SHCLK signal high.
Intel^® 82801DB ICH4 Datasheet
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