82801DB Datasheet, PDF (269/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LAN Controller Registers (B1:D8:F0)
7.2.7
Receive DMA Byte Count Register
Offset Address: 14–17h
Default Value: 0000 0000h
Attribute:
Size:
RO
32 bits
Bit
Description
31:0
Receive DMA Byte Count — RO. Keeps track of how many bytes of receive data have been
passed into host memory via DMA.
7.2.8 Early Receive Interrupt Register
Offset Address: 18h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
The Early Receive Interrupt register allows the internal LAN controller to generate an early
interrupt depending on the length of the frame. The LAN controller will generate an interrupt at the
end of the frame regardless of whether or not Early Receive Interrupts are enabled.
Note:
It is recommended that software not utilize this register unless receive interrupt latency is a critical
performance issue in that particular software environment. Using this feature may reduce receive
interrupt latency, but will also result in the generation of more interrupts, that can degrade system
efficiency and performance in some environments.
Bit
Description
Early Receive Count — R/W. When some non-zero value x is programmed into this register, the
LAN controller will set the ER bit in the SCB Status Word Register and assert INTA# when the byte
7:0 count indicates that there are x quad-words remaining to be received in the current frame (based on
the Type/Length field of the received frame). No Early Receive interrupt will be generated if a value
of 00h (the default value) is programmed into this register.
Intel^® 82801DB ICH4 Datasheet
269