82801DB Datasheet, PDF (575/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Register Index
Table A-3. Intel^® ICH4 Variable I/O Registers (Sheet 3 of 6)
Register Name
Offset
Datasheet Location
BMIDE I/O Registers at BM_BASE + Offset
BM_BASE is set at Section 10.1.12, “SCMD_BAR—Secondary Command Block Base Address Register (IDE D31:F1)” on
page 10-388
Command Register Primary
Status Register Primary
Descriptor Table Pointer Primary
Command Register Secondary
Status Register Secondary
Descriptor Table Pointer
Secondary
00h
02h
04–07h
08h
0Ah
0C–0Fh
Section 10.2.1, “BMIC[P,S]—Bus Master IDE Command Register” on
page 10-397
Section 10.2.2, “BMIS[P,S]—Bus Master IDE Status Register” on
page 10-398
Section 10.2.3, “BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register” on page 10-398
Section 10.2.1, “BMIC[P,S]—Bus Master IDE Command Register” on
page 10-397
Section 10.2.2, “BMIS[P,S]—Bus Master IDE Status Register” on
page 10-398
Section 10.2.3, “BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register” on page 10-398
USB I/O Registers at Base Address + Offset
USB Base Address is set at Section 11.1.10, “BASE—Base Address Register (USB—D29:F0/F1/F2)” on page 11-403
USB Command Register
USB Status Register
USB Interrupt Enable
USB Frame Number
USB Frame List Base Address
USB Start of Frame Modify
Port 0, 2, 4 Status/Control
Port 1, 3, 5 Status/Control
00–01h
02–03h
04–05h
06–07h
08–0Bh
0Ch
10–11h
12–13h
Section 11.2.1, “USBCMD—USB Command Register” on page 11-408
Section 11.2.2, “USBSTS—USB Status Register” on page 11-411
Section 11.2.3, “USBINTR—Interrupt Enable Register” on page 11-412
Section 11.2.4, “FRNUM—Frame Number Register” on page 11-412
Section 11.2.5, “FRBASEADD—Frame List Base Address” on page 11-413
Section 11.2.6, “SOFMOD—Start of Frame Modify Register” on page 11-414
Section 11.2.7, “PORTSC[0,1]—Port Status and Control Register” on
page 11-415
Section 11.2.7, “PORTSC[0,1]—Port Status and Control Register” on
page 11-415
SMBus I/O Registers at SMB_BASE + Offset
SMB_BASE is set at Section 13.1.8, “SMB_BASE—SMBUS Base Address Register (SMBUS—D31:F3)” on page 13-453
Host Status
Host Control
Host Command
Transmit Slave Address
Host Data 0
Host Data 1
Block Data Byte
Packet Error Check
Receive Slave Address
Receive Slave Data
00h
Section 13.2.1, “HST_STS—Host Status Register” on page 13-456
02h
Section 13.2.2, “HST_CNT—Host Control Register” on page 13-458
03h
Section 13.2.3, “HST_CMD—Host Command Register” on page 13-459
04h
Section 13.2.4, “XMIT_SLVA—Transmit Slave Address Register” on
page 13-459
05h
Section 13.2.5, “HST_D0—Data 0 Register” on page 13-459
06h
Section 13.2.6, “HST_D1—Data 1 Register” on page 13-460
07h
Section 13.2.7, “Host_BLOCK_DB—Host Block Data Byte Register” on
page 13-460
08h
Section 13.2.8, “PEC—Packet Error Check (PEC) Register” on page 13-460
09h
Section 13.2.9, “RCV_SLVA—Receive Slave Address Register” on
page 13-461
0Ah
Section 13.2.10, “SLV_DATA—Receive Slave Data Register” on
page 13-461
Intel^® 82801DB ICH4 Datasheet
575