82801DB Datasheet, PDF (352/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.8.2 APM I/O Decode
Table 9-9 shows the I/O registers associated with APM support. This register space is enabled in
the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved (fixed I/O location).
Table 9-9. APM Register Map
Address
B2h
B3h
Mnemonic
APM_CNT
APM_STS
Register Name
Advanced Power Management Control Port
Advanced Power Management Status Port
Default
00h
00h
Type
R/W
R/W
9.8.2.1
APM_CNT—Advanced Power Management Control Port Register
I/O Address:
Default Value:
Lockable:
Power Well:
B2h
00h
No
Core
Attribute:
Size:
Usage:
R/W
8 bit
Legacy Only
9.8.2.2
Bit
Description
7:0
Used to pass an APM command between the OS and the SMI handler. Writes to this port not only
store data in the APMC register, but also generates an SMI# when the APMC_EN bit is set.
APM_STS—Advanced Power Management Status Port Register
I/O Address:
Default Value:
Lockable:
Power Well:
B3h
00h
No
Core
Attribute:
Size:
Usage:
R/W
8 bit
Legacy Only
Bit
Description
7:0
Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad register and
is not affected by any other register or function (other than a PCI reset).
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Intel^® 82801DB ICH4 Datasheet