HD6432345 Datasheet, PDF (93/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

3.2.2 System Control Register (SYSCR)
Bit
:
7
—
Initial value:
0
R/W
: R/W
6
5
4
3
2
— INTM1 INTM0 NMIEG —
0
0
0
0
0
R/W R/W R/W R/W R/W
1
0
— RAME
0
1
R/W R/W
Bits 7 and 6—Reserved: Only 0 should be written to these bits.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control
mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,
Interrupt Control Modes and Interrupt Operation.
Bit 5
INTM1
0
1
Bit 4
INTM0
0
1
0
1
Interrupt
Control Mode
0
—
2
—
Description
Control of interrupts by I bit
(Initial value)
Setting prohibited
Control of interrupts by I2 to I0 bits and IPR
Setting prohibited
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG
0
1
Description
An interrupt is requested at the falling edge of NMI input
An interrupt is requested at the rising edge of NMI input
(Initial value)
Bits 2 and 1—Reserved: Only 0 should be written to these bits.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset status is released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
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