HD6432345 Datasheet, PDF (593/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

17.10 Flash Memory Protection
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
17.10.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1
and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2). (See table 17.16.)
Table 17.16 Hardware Protection
Functions
Item
Description
Program Erase Verify*
FWE pin
• When a low level is input to the FWE pin, ^No
No
No
protection
FLMCR1, FLMCR2 (excluding the FLER
bit), EBR1, and EBR2 are initialized, and
the program/erase-protected state is
entered.
Reset/standby • In a reset (including a WDT overflow reset) No
No
No
protection
and in standby mode, FLMCR1, FLMCR2,
EBR1, and EBR2 are initialized, and the
program/erase-protected state is entered.
• In a reset via the RES pin, the reset state
is not entered unless the RES pin is held
low until oscillation stabilizes after
powering on. In the case of a reset during
operation, hold the RES pin low for the
RES pulse width (t ) _RESW specified in the AC
Characteristics section.
Note: * Program verify and erase verify modes.
17.10.2 Software Protection
Software protection can be implemented by setting the SWE bit in FLMCR1, erase block registers
1 and 2 (EBR1, EBR2), and the RAMS bit in RAMER. When software protection is in effect,
setting the P or E bit in flash memory control register 1 (FLMCR1) does not cause a transition to
program mode or erase mode. (See table 17.17.)
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