HD6432345 Datasheet, PDF (822/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

SCR0—Serial Control Register 0
H'FF7A
Smart Card Interface 0
Bit
:
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE MPIE TEIE CKE1 CKE0
Initial value :
0
0
0
0
0
0
0
0
Read/Write : R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Enable
SMCR SMR SCR setting
SMIF C/A,GM CKE1 CKE0
SCK pin function
0
See SCI specification
1
0
0
0 ^{Operates as port input}
pin
1
0
0
1
Clock output as SCK
output pin
1
1
0
0 ^{Fixed-low output as}
SCK output pin
1
1
0
1
Clock output as SCK
output pin
1
1
1
0 ^{Fixed-high output as}
SCK output pin
1
1
1
1 ^{Clock output as SCK}
output pin
Transmit End Interrupt Enable
0 Transmit end interrupt (TEI) request disabled
1 Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable
0 Multiprocessor interrupts disabled
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When MPB= 1 data is received
1 Multiprocessor interrupts enabled
Receive interrupt (RXI) requests, receive error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in
SSR are disabled until data with the multiprocessor bit set to 1
is received
Receive Enable
0 Reception disabled
1 Reception enabled
Transmit Enable
0 Transmission disabled
1 Transmission enabled
Receive Interrupt Enable
0 Receive data full interrupt (RXI) request and
receive error interrupt (ERI) request disabled
1 Receive data full interrupt (RXI) request and
receive error interrupt (ERI) request enabled
Transmit Interrupt Enable
0 Transmit data empty interrupt (TXI) requests disabled
1 Transmit data empty interrupt (TXI) requests enabled
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