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HD6432345 Datasheet, PDF (426/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual | |||
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⢠Full-duplex communication capability
 The transmitter and receiver are mutually independent, enabling transmission and reception
to be executed simultaneously
 Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data
⢠On-chip baud rate generator allows any bit rate to be selected
⢠Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK pin
⢠Four interrupt sources
 Four interrupt sources â transmit-data-empty, transmit-end, receive-data-full, and receive
error â that can issue requests independently
 The transmit-data-empty interrupt and receive data full interrupts can activate the data
transfer controller (DTC) to execute data transfer
⢠Choice of LSB-first or MSB-first transfer
 Can be selected regardless of the communication mode* (except in the case of
asynchronous mode bit data)
⢠Module stop mode can be set
 As the initial setting, SCI operation is halted. Register access is enabled by exiting module
stop mode.
Note: * Descriptions in this section refer to LSB-first transfer.
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