HD6432345 Datasheet, PDF (547/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

16.1.1 Block Diagram
Figure 16.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FFEC00
H'FFEC02
H'FFEC04
H'FFEC01
H'FFEC03
H'FFEC05
H'FFFBFE
H'FFFBFF
Figure 16.1 Block Diagram of RAM (H8S/2345, Advanced Mode)
16.1.2 Register Configuration
The on-chip RAM is controlled by SYSCR. Table 16.1 shows the address and initial value of
SYSCR.
Table 16.1 RAM Register
Name
Abbreviation R/W
System control register
SYSCR
R/W
Note: * Lower 16 bits of the address.
Initial Value
H'01
Address*
H'FF39
534