HD6432345 Datasheet, PDF (773/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

TMDR3—Timer Mode Register 3
H'FE81
Bit
:
7
—
Initial value :
1
Read/Write :
—
6
5
4
3
2
1
0
—
BFB BFA MD3 MD2 MD1 MD0
1
0
0
0
0
0
0
—
R/W R/W R/W R/W R/W R/W
TPU3
Mode
0 0 0 0 Normal operation
1 Reserved
1 0 PWM mode 1
1 PWM mode 2
1 0 0 Phase counting mode 1
1 Phase counting mode 2
1 0 Phase counting mode 3
1 Phase counting mode 4
1 * * *—
* : Don’t care
Notes: 1. MD3 is a reserved bit. In a write,
it should always be written with 0.
2. Phase counting mode cannot be
set for channels 0 and 3. In this
case, 0 should always be written
to MD2.
Buffer Operation A
0 TGRA operates normally
1 ^{TGRA and TGRC used together}
for buffer operation
Buffer Operation B
0 TGRB operates normally
1 ^{TGRB and TGRD used together}
for buffer operation
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