HD6432345 Datasheet, PDF (69/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table 2.3 Instructions Classified by Function (cont)
Type
Instruction
System control TRAPA
instructions _RTE
SLEEP
LDC
Size*
—
—
—
B/W
STC
B/W
ANDC
B
ORC
B
XORC
B
NOP
—
Note: * Size refers to the operand size.
B: Byte
W: Word
Function
Starts trap-instruction exception handling.
Returns from an exception-handling routine.
Causes a transition to a power-down state.
(EAs) → CCR, (EAs) → EXR
Moves the source operand contents or immediate data
to CCR or EXR. Although CCR and EXR are 8-bit
registers, word-size transfers are performed between
them and memory. The upper 8 bits are valid.
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or
memory. Although CCR and EXR are 8-bit registers,
word-size transfers are performed between them and
memory. The upper 8 bits are valid.
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with
immediate data.
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate
data.
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with
immediate data.
PC + 2 → PC
Only increments the program counter.
49