HD6432345 Datasheet, PDF (92/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

3.1.3 Register Configuration
The H8S/2345 Series has a mode control register (MDCR) that indicates the inputs at the mode
pins (MD₂ to MD₀), and a system control register (SYSCR) and a system control register 2
(SYSCR2)*² that control the operation of the H8S/2345 Series. Table 3.3 summarizes these
registers.
Table 3.3 MCU Registers
Name
Abbreviation
R/W
Initial Value
Address*¹
Mode control register
MDCR
R
Undetermined
H'FF3B
System control register
SYSCR
R/W
H'01
H'FF39
System control register 2*² SYSCR2
R/W
H'00
H'FF42
Notes: 1. Lower 16 bits of the address.
2. The SYSCR2 register can only be used in the F-ZTAT version. In the ZTAT, mask
ROM, and ROMless versions, this register cannot be written to and will return an
undefined value of read.
3.2 Register Descriptions
3.2.1 Mode Control Register (MDCR)
Bit
:
7
6
5
4
—
—
—
—
Initial value:
1
0
0
0
R/W
:
—
—
—
—
3
2
1
0
— MDS2 MDS1 MDS0
0
—*
—*
—*
—
R
R
R
Note: * Determined by pins MD₂ to MD₀.
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2345
Series.
Bit 7—Reserved: Read-only bit, always read as 1.
Bits 6 to 3—Reserved: Read-only bits, always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins
MD₂ to MD₀ (the current operating mode). Bits MDS2 to MDS0 correspond to MD₂ to MD₀.
MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD₂ to MD₀) input
levels are latched into these bits when MDCR is read. These latches are canceled by a power-on
reset, but are retained after a manual reset.
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