HD6432345 Datasheet, PDF (413/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

11.2 Register Descriptions
11.2.1 Timer Counter (TCNT)
Bit
:
7
6
5
4
3
2
1
0
Initial value :
0
R/W
: R/W
0
0
R/W R/W
0
0
0
R/W R/W R/W
0
0
R/W R/W
TCNT is an 8-bit readable/writable*¹ up-counter.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), either the watchdog timer overflow signal (WDTOVF)*² or an interval timer
interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR.
TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared
to 0. It is not initialized in software standby mode.
Note: 1. The method for writing to TCNT is different from that for general registers to prevent
inadvertent overwriting. For details see section 11.2.4, Notes on Register Access.
2. The WDTOVF pin function is not supported by the F-ZTAT version.
11.2.2 Timer Control/Status Register (TCSR)
Bit
:
7
6
5
4
OVF WT/IT TME
—
Initial value :
0
0
0
1
R/W
: R/(W)* R/W R/W
—
3
2
1
0
—
CKS2 CKS1 CKS0
1
0
0
0
—
R/W
R/W
R/W
Note: * Can only be written with 0 for flag clearing.
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software
standby mode.
Note: * The method for writing to TCSR is different from that for general registers to prevent
inadvertent overwriting. For details see section 11.2.4, Notes on Register Access.
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