HD6432345 Datasheet, PDF (312/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

• TIOR0L
Bit 7 Bit 6 Bit 5 Bit 4
Channel IOD3 IOD2 IOD1 IOD0 Description
0
0 0 0 0 TGR0D is Output disabled
(Initial value)
1
output _{Initial output is 0 0 output at compare match}
1
0
compare _output
register*²
1 output at compare match
1
Toggle output at compare
match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1 0 0 0 TGR0D is Capture input Input capture at rising edge
1
input
source is
Input capture at falling edge
capture TIOCD0 pin
1
*
register*²
Input capture at both edges
1
*
*
Capture input Input capture at TCNT1
source is channel count-up/count-down*¹
1/count clock
*: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the TCNT1
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
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