HD6432345 Datasheet, PDF (392/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Bit 6—Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt
requests (CMIA) are enabled or disabled when the CMFA flag of TCSR is set to 1.
Bit 6
CMIEA
0
1
Description
CMFA interrupt requests (CMIA) are disabled
CMFA interrupt requests (CMIA) are enabled
(Initial value)
Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether OVF interrupt requests
(OVI) are enabled or disabled when the OVF flag of TCSR is set to 1.
Bit 5
OVIE
0
1
Description
OVF interrupt requests (OVI) are disabled
OVF interrupt requests (OVI) are enabled
(Initial value)
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select the method by
which TCNT is cleared: by compare match A or B, or by an external reset input.
Bit 4
CCLR1
0
1
Bit 3
CCLR0
0
1
0
1
Description
Clear is disabled
Clear by compare match A
Clear by compare match B
Clear by rising edge of external reset input
(Initial value)
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to
TCNT is an internal or external clock.
Three internal clocks can be selected, all divided from the system clock (ø): ø/8, ø/64, and ø/8192.
The falling edge of the selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
Some functions differ between channel 0 and channel 1.
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