HD6432345 Datasheet, PDF (202/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Table 7.2 outlines the functions of the DTC.
Table 7.2 DTC Functions
Transfer Mode
• Normal mode
 One transfer request transfers one
byte or one word
 Memory addresses are incremented
or decremented by 1 or 2
 Up to 65,536 transfers possible
• Repeat mode
 One transfer request transfers one
byte or one word
 Memory addresses are incremented
or decremented by 1 or 2
 After the specified number of
transfers (1 to 256), the initial state
resumes and operation continues
• Block transfer mode
 One transfer request transfers a block
of the specified size
 Block size is from 1 to 256 bytes or
words
 Up to 65,536 transfers possible
 A block area can be designated at
either the source or destination
Activation Source
• IRQ
• TPU TGI
• 8-bit timer CMI
• SCI TXI or RXI
• A/D converter ADI
• Software
Address Registers
Transfer Transfer
Source Destination
24 bits
24 bits
184