HD6432345 Datasheet, PDF (88/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Bus cycle
T1
T2
ø
Address bus
AS
RD
HWR, LWR
Data bus
Unchanged
High
High
High
High-impedance state
Figure 2.20 Pin States during On-Chip Supporting Module Access
2.9.4 External Address Space Access Timing
The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or
three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to
section 6, Bus Controller.
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