HD6432345 Datasheet, PDF (589/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

reprogram data area written consecutively to the write addresses. The lower 8 bits of the first
address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. Thirty-two
consecutive byte data transfers are performed. The program address and program data are latched
in the flash memory. A 32-byte data transfer must be performed even if writing fewer than 32
bytes; in this case, H'FF data must be written to the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set a value greater than (y + z + α + ß) µs as the WDT overflow period. After this, preparation for
program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the
elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in
FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a
program setting so that the time for one programming operation is within the range of (z) µs.
17.9.2 Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the P bit in
FLMCR1 is cleared to 0, then the PSU bit in FLMCR2 is cleared to 0 at least (α) µs later). Next,
the watchdog timer is cleared after the elapse of (y + z + α + β) µs or more, and the operating
mode is switched to program-verify mode by setting the PV bit in FLMCR1. Before reading in
program-verify mode, a dummy write of H'FF data should be made to the addresses to be read.
The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is
read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at
least (ε) µs after the dummy write before performing this read operation. Next, the originally
written data is compared with the verify data, and reprogram data is computed (see figure 17.21)
and transferred to the reprogram data area. After 32 bytes of data have been verified, exit program-
verify mode, wait for at least (η) µs, then clear the SWE bit in FLMCR1 to 0. If reprogramming is
necessary, set program mode again, and repeat the program/program-verify sequence as before.
However, ensure that the program/program-verify sequence is not repeated more than (N) times on
the same bits.
Note: An area in RAM for storing write data (32 bytes) and an area for storing rewrite data (32
bytes) are required.
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