HD6432345 Datasheet, PDF (256/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

• Mode 6*
Setting a PADDR bit to 1 makes the corresponding port A pin an address output while clearing
the bit to 0 makes the pin an input port.
Port A Data Register (PADR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
—
—
—
— PA3DR
Undefined Undefined Undefined Undefined 0
—
—
—
—
R/W
2
PA2DR
0
R/W
1
PA1DR
0
R/W
0
PA0DR
0
R/W
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA₃ to
PA₀).
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
PADR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Port A Register (PORTA)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
—
PA3
PA2
PA1
PA0
Initial value : Undefined Undefined Undefined Undefined —*
—*
—*
—*
R/W
:
—
—
—
—
R
R
R
R
Note: * Determined by state of pins PA3 to PA0.
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA₃ to PA₀) must always be performed on PADR.
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A
read is performed while PADDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin
states, as PADDR and PADR are initialized. PORTA retains its prior state after a manual reset,
and in software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
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