HD6432345 Datasheet, PDF (668/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Bus Timing: Table 20.16 lists the bus timing.
Table 20.16 Bus Timing
Condition A: V_CC = AV_CC = 2.7 to 5.5 V, V_ref = 2.7 V to AV_CC, V_SS = AV_SS = 0 V,
ø = 2 to 10 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition B: V_CC = AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC, V_SS = AV_SS = 0 V,
ø= 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Item
Address delay time
Address setup time
Symbol
t _AD
t _AS
Address hold time
t _AH
CS delay time 1
AS delay time
RD delay time 1
RD delay time 2
CAS delay time
Read data setup time
Read data hold time
Read data access
time 1
t _CSD1
t _ASD
t _RSD1
t _RSD2
t _CASD
t _RDS
t _RDH
t _ACC1
Read data access
t _ACC2
time 2
Read data access
t _ACC3
time 3
Read data access
t _ACC4
time 4
Read data access
t _ACC5
time 5
Condition A
Min Max
—
40
0.5 × —
t_cyc – 30
0.5 × —
t_cyc – 20
—
40
—
40
—
40
—
40
—
40
30
—
0
—
—
1.0 ×
t_cyc – 50
—
1.5 ×
t_cyc – 50
—
2.0 ×
t_cyc – 50
—
2.5 ×
t_cyc – 50
—
3.0 ×
t_cyc – 50
Condition B
Min Max Unit
—
20
ns
0.5 × —
ns
t_cyc – 15
0.5 × —
ns
t_cyc – 10
—
20
ns
—
20
ns
—
20
ns
—
20
ns
—
20
ns
15
—
ns
0
—
ns
—
1.0 × ns
t_cyc – 25
—
1.5 × ns
t_cyc – 25
—
2.0 × ns
t_cyc – 25
—
2.5 × ns
t_cyc – 25
—
3.0 × ns
t_cyc – 25
Test Conditions
Figure 20.11 to
Figure 20.15
659