HD6432345 Datasheet, PDF (755/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table A.6 Instruction Execution Cycles (cont)
Instruction
XOR.L ERs,ERd
XORC #xx:8,CCR
XORC #xx:8,EXR
Reset exception
handling
Interrupt exception
handling
1
R:W 2nd
R:W NEXT
R:W 2nd
R:W:M VEC
R:W^*6
2
3
4
R:W NEXT
R:W NEXT
R:W VEC+2 Internal operation, R:W^*5
1 state
Internal operation, W:W stack (L) W:W stack (H)
1 state
5
6
7
8
9
W:W stack (EXR) R:W:M VEC R:W VEC+2 Internal operation, R:W^*7
1 state
Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6.
2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial
value of R4L or R4. If n = 0, these bus cycles are not executed.
3. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers.
4. Start address after return.
5. Start address of the program.
6. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read
operation is replaced by an internal operation.
7. Start address of the interrupt-handling routine.