HD6432345 Datasheet, PDF (16/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

13.3.4 Register Settings................................................................................................... 486
13.3.5 Clock .................................................................................................................... 488
13.3.6 Data Transfer Operations ..................................................................................... 490
13.3.7 Operation in GSM Mode...................................................................................... 497
13.4 Usage Note ........................................................................................................................ 498
Section 14 A/D Converter ................................................................................................. 503
14.1 Overview............................................................................................................................ 503
14.1.1 Features ................................................................................................................ 503
14.1.2 Block Diagram...................................................................................................... 504
14.1.3 Pin Configuration ................................................................................................. 505
14.1.4 Register Configuration ......................................................................................... 506
14.2 Register Descriptions......................................................................................................... 507
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 507
14.2.2 A/D Control/Status Register (ADCSR)................................................................ 508
14.2.3 A/D Control Register (ADCR)............................................................................. 510
14.2.4 Module Stop Control Register (MSTPCR) .......................................................... 511
14.3 Interface to Bus Master...................................................................................................... 512
14.4 Operation ........................................................................................................................... 513
14.4.1 Single Mode (SCAN = 0) ..................................................................................... 513
14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 515
14.4.3 Input Sampling and A/D Conversion Time.......................................................... 517
14.4.4 External Trigger Input Timing ............................................................................. 518
14.5 Interrupts............................................................................................................................ 519
14.6 Usage Notes ....................................................................................................................... 519
Section 15 D/A Converter ................................................................................................. 525
15.1 Overview............................................................................................................................ 525
15.1.1 Features ................................................................................................................ 525
15.1.2 Block Diagram...................................................................................................... 526
15.1.3 Pin Configuration ................................................................................................. 527
15.1.4 Register Configuration ......................................................................................... 527
15.2 Register Descriptions......................................................................................................... 528
15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 528
15.2.2 D/A Control Register (DACR)............................................................................. 528
15.2.3 Module Stop Control Register (MSTPCR) .......................................................... 530
15.3 Operation ........................................................................................................................... 531
15.4 Usage Notes ....................................................................................................................... 532
Section 16 RAM ................................................................................................................... 533
16.1 Overview............................................................................................................................ 533
16.1.1 Block Diagram...................................................................................................... 534
16.1.2 Register Configuration ......................................................................................... 534
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