HD6432345 Datasheet, PDF (818/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

SMR0—Serial Mode Register 0
Bit
:
7
6
5
C/A
CHR
PE
Initial value :
0
0
0
Read/Write : R/W
R/W R/W
H'FF78
SCI0
4
3
2
1
0
O/E STOP MP CKS1 CKS0
0
0
0
0
0
R/W R/W
R/W
R/W
R/W
Clock Select
0 0 ø clock
1 ø/4 clock
1 0 ø/16 clock
1 ø/64 clock
Multiprocessor Mode
0 Multiprocessor function disabled
1 Multiprocessor format selected
Stop Bit Length
0 1 stop bit
1 2 stop bits
Parity Mode
0 Even parity
1 Odd parity
Parity Enable
0 Parity bit addition and checking disabled
1 Parity bit addition and checking enabled
Character Length
0 8-bit data
1 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
Asynchronous Mode/Synchronous Mode Select
0 Asynchronous mode
1 Synchronous mode
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