HD6432345 Datasheet, PDF (625/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table 18.4 External Clock Input Conditions
V_CC = 2.7 V* V_CC = 5.0 V
to 5.5 V
± 10%
Item
Test
Symbol Min Max Min Max Unit Conditions
External clock input
t _EXL
low pulse width
40 —
20 — ns Figure 18.6
External clock input
t _EXH
high pulse width
40 —
20 — ns
External clock rise time t_EXr
External clock fall time t_EXf
Clock low pulse width t_CL
level
— 10
— 10
0.4 0.6
80 —
— 5 ns
— 5 ns
0.4 0.6 t_cyc
80 — ns
ø ≥ 5 MHz Figure 20.4
ø < 5 MHz
Clock high pulse width t_CH
level
0.4 0.6
80 —
0.4 0.6 t_cyc
80 — ns
ø ≥ 5 MHz
ø < 5 MHz
Note: * ZTAT, mask ROM, and ROMless versions only.
t_EXH
t_EXL
EXTAL
V_CC × 0.5
t_EXr
t_EXf
Figure 18.6 External Clock Input Timing
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