HD6432345 Datasheet, PDF (54/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Some instructions leave some or all of the flag bits unchanged. For the action of each instruction
on the flag bits, refer to Appendix A.1, List of Instructions.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
2.4.4 Initial Register Values
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.
The stack pointer should therefore be initialized by an MOV.L instruction executed immediately
after a reset.
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