HD6432345 Datasheet, PDF (603/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table 17.20 Settings for Each Operating Mode in Writer Mode
Mode
FWE
CE
Read
H or L
L
Output disable H or L
L
Command write H or L*³ L
Chip disable*¹
H or L
H
Legend:
H: High level
L: Low level
X: Don’t care
Hi-z: High impedance
Pin Names
OE
WE
FO₀ to FO₇ FA₀ to FA₁₆
L
H
Data output Ain
H
H
Hi-z
X
H
L
Data input Ain*²
X
X
Hi-z
X
Notes: 1. Chip disable is not a standby state; internally, it is an operation state.
2. Ain indicates that there is also address input in auto-program mode.
3. For command writes when making a transition to auto-program or auto-erase mode,
input a high level to the FWE pin.
Table 17.21 Writer Mode Commands
Command Name
Number
of Cycles Mode
Memory read mode 1 + n*¹
Write
Auto-program mode 129*²
Write
Auto-erase mode
2
Write
Status read mode 2
Write
Legend:
RA: Read address
WA: Program address (Write address)
Dout: Read data
Din: Program data
1st Cycle
Address Data
X
H'00
X
H'40
X
H'20
X
H'71
Mode
Read
Write
Write
Write
2nd Cycle
Address Data
RA
Dout
WA
Din
X
H'20
X
H'71
Notes: 1. In memory read mode, the number of cycles depends on the number of address write
cycles (n).
2. In auto-program mode. 129 cycles are required for command writing by a simultaneous
128-byte write.
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