HD6432345 Datasheet, PDF (380/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Contention between TGR Write and Compare Match: If a compare match occurs in the T2
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written.
Figure 9.51 shows the timing in this case.
ø
Address
TGR write cycle
T1
T2
TGR address
Write signal
Compare
match signal
TCNT
Inhibited
N
N+1
TGR
N
M
TGR write data
Figure 9.51 Contention between TGR Write and Compare Match
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