HD6432345 Datasheet, PDF (261/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

8.7.2 Register Configuration
Table 8.11 shows the port B register configuration.
Table 8.11 Port B Registers
Name
Abbreviation R/W
Port B data direction register
PBDDR
W
Port B data register
PBDR
R/W
Port B register
PORTB
R
Port B MOS pull-up control register PBPCR
R/W
Note: * Lower 16 bits of the address.
Initial Value
H'00
H'00
Undefined
H'00
Address *
H'FEBA
H'FF6A
H'FF5A
H'FF71
Port B Data Direction Register (PBDDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to
select whether the address output pins retain their output state or become high-impedance when a
transition is made to software standby mode.
• Modes 1, 4, and 5*
The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits.
• Modes 2 and 6*
Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while
clearing the bit to 0 makes the pin an input port.
• Modes 3 and 7*
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing
the bit to 0 makes the pin an input port.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
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