HD6432345 Datasheet, PDF (762/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Appendix B Internal I/O Register
B.1 Addresses
Address Register
(low) Name Bit 7
H’F800 MRA SM1
to
SAR
H’FBFF
Bit 6
SM0
Bit 5
DM1
Bit 4
DM0
Bit 3
MD1
Bit 2
MD0
Bit 1
DTS
Bit 0
Sz
Module Name
DTC
Data Bus
Width
16/32* bit
MRB CHNE DISEL —
—
—
—
—
—
DAR
CRA
CRB
H’FE80 TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU3
16 bit
H’FE81 TMDR3 —
—
BFB BFA MD3 MD2 MD1 MD0
H’FE82 TIOR3H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
H’FE83 TIOR3L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0
H’FE84 TIER3 TTGE —
—
TCIEV TGIED TGIEC TGIEB TGIEA
H’FE85 TSR3 —
—
—
TCFV TGFD TGFC TGFB TGFA
H’FE86 TCNT3
H’FE87
H’FE88 TGR3A
H’FE89
H’FE8A TGR3B
H’FE8B
H’FE8C TGR3C
H’FE8D
H’FE8E TGR3D
H’FE8F
Note: * Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as
register information, and 16 bits otherwise.
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