HD6432345 Datasheet, PDF (148/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

5.6.3 Operation
The interrupt controller has three main functions in DTC control.
(1) Selection of Interrupt Source: Interrupt sources can be specified as DTC activation requests
or CPU interrupt requests by means of the DTCE bit of DTCEA to DTCEE in the DTC.
After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the
CPU in accordance with the specification of the DISEL bit of MRB in the DTC.
When the DTC has performed the specified number of data transfers and the transfer counter value
is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data
transfer.
(2) Determination of Priority: The DTC activation source is selected in accordance with the
default priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC
Vector Table, for the respective priorities.
(3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
If the same interrupt is selected as a DTC activation source or CPU interrupt source, operations are
performed for them independently according to their respective operating statuses and bus
mastership priorities.
Table 5.11 summarizes interrupt source selection and interrupt source clearance control according
to the settings of the DTCE bit of DTCEA to DTCEE in the DTC and the DISEL bit of MRB in
the DTC.
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