HD6432345 Datasheet, PDF (653/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Timing of On-Chip Supporting Modules: Table 20.7 lists the timing of on-chip supporting
modules.
Table 20.7 Timing of On-Chip Supporting Modules
Condition A: —In planning stage—
V_CC = AV_CC = 3.0 V to 5.5 V, V_ref = 3.0 V to AV_CC, V_SS = AV_SS = 0 V,
ø = 2 to 10 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition B: V_CC = AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC, V_SS = AV_SS = 0 V,
ø = 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Item
Symbol
I/O port Output data delay t_PWD
time
Input data setup t_PRS
time
Input data hold
t _PRH
time
TPU
Timer output delay t_TOCD
time
Timer input setup t_TICS
time
Timer clock input t_TCKS
setup time
Timer
clock
pulse
width
Single
edge
Both
edges
t _TCKWH
t _TCKWL
8-bit timer Timer output delay t_TMOD
time
Timer reset input
setup time
t _TMRS
Timer clock input t_TMCS
setup time
Timer
clock
pulse
width
Single
edge
Both
edges
t _TMCWH
t _TMCWL
Condition A
Min Max
— 100
50 —
50 —
— 100
50 —
50 —
1.5 —
2.5 —
— 100
50 —
50 —
1.5 —
2.5 —
Condition B
Min Max Unit
— 50
ns
30 —
30 —
— 50
ns
30 —
30 —
ns
1.5 —
t _cyc
2.5 —
— 50
ns
30 —
ns
30 —
ns
1.5 —
t _cyc
2.5 —
Test Conditions
Figure 20.17
Figure 20.18
Figure 20.19
Figure 20.20
Figure 20.22
Figure 20.21
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