HD6432345 Datasheet, PDF (639/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Oscillator
RES
STBY
Oscillation
stabilization
time
Reset
exception
handling
Figure 19.3 Hardware Standby Mode Timing (Example)
19.8 ø Clock Output Disabling Function
Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the ø clock stops at the end of the bus cycle,
and ø output goes high. ø clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, ø clock output is disabled and input port mode is set.
Table 19.5 shows the state of the ø pin in each processing state.
Table 19.5 ø Pin State in Each Processing State
DDR
PSTOP
Hardware standby mode
Software standby mode
Sleep mode
Normal operating state
0
—
High impedance
High impedance
High impedance
High impedance
1
0
Fixed high
ø output
ø output
1
Fixed high
Fixed high
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