HD6432345 Datasheet, PDF (226/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

8.2.2 Register Configuration
Table 8.2 shows the port 1 register configuration.
Table 8.2 Port 1 Registers
Name
Abbreviation R/W
Port 1 data direction register
P1DDR
W
Port 1 data register
P1DR
R/W
Port 1 register
PORT1
R
Note: * Lower 16 bits of the address.
Initial Value
H'00
H'00
Undefined
Address*
H'FEB0
H'FF60
H'FF50
Port 1 Data Direction Register (P1DDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read.
Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P1DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. As the TPU is initialized by a
manual reset, the pin states are determined by the P1DDR and P1DR specifications.
Whether the address output pins maintain their output state or go to the high-impedance state in a
transition to software standby mode is selected by the OPE bit in SBYCR.
• Modes 1 to 3 and 7*
The corresponding port 1 pins are output ports when P1DDR is set to 1, and input ports when
cleared to 0.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
209