HD6432345 Datasheet, PDF (709/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table A.1 Instruction Set
(8) Block Transfer Instructions
Addressing Mode/
Instruction Length (Bytes)
Mnemonic
EEPMOV EEPMOV.B
—
Operation
4 if R4L≠0
Repeat @ER5→@ER6
ER5+1→ER5
ER6+1→ER6
R4L-1→R4L
Until R4L=0
else next;
Condition Code No. of States*¹
I H N Z V C Advanced
——————
4+2n *²
EEPMOV.W
—
4 ^{if R4≠0}
Repeat @ER5→@ER6
ER5+1→ER5
ER6+1→ER6
R4-1→R4
Until R4=0
else next;
——————
4+2n *²
Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory.
2. n is the initial value of R4L or R4.
[1] Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers.
[2] Cannot be used in the H8S/2345 Series.
[3] Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
[4] Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
[5] Retains its previous value when the result is zero; otherwise cleared to 0.
[6] Set to 1 when the divisor is negative; otherwise cleared to 0.
[7] Set to 1 when the divisor is zero; otherwise cleared to 0.
[8] Set to 1 when the quotient is negative; otherwise cleared to 0.
[9] One additional state is required for execution when EXR is valid.