HD6432345 Datasheet, PDF (159/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read cycles are performed in different areas.
Bit 7
ICIS1
0
1
Description
Idle cycle not inserted in case of successive external read cycles in different areas
Idle cycle inserted in case of successive external read cycles in different areas
(Initial value)
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read and external write cycles are performed .
Bit 6
ICIS0
0
1
Description
Idle cycle not inserted in case of successive external read and external write cycles
Idle cycle inserted in case of successive external read and external write cycles
(Initial value)
Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM
interface. In normal mode*, the selection can be made from the entire external space .
Burst ROM interface and PSRAM burst operation cannot be set at the same time.
Note: * ZTAT, mask ROM, and ROMless versions only.
Bit 5
BRSTRM
0
1
Description
Area 0 is basic bus interface
Area 0 is burst ROM interface
(Initial value)
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 4
BRSTS1
0
1
Description
Burst cycle comprises 1 state
Burst cycle comprises 2 states
(Initial value)
140