HD6432345 Datasheet, PDF (482/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

12.4 SCI Interrupts
The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt
(ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI)
request. Table 12.12 shows the interrupt sources and their relative priorities. Individual interrupt
sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of
interrupt request is sent to the interrupt controller independently.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to
perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is
performed by the DTC. The DTC cannot be activated by a TEI interrupt request.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can
activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data
transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request.
Table 12.12 SCI Interrupt Sources
Interrupt
Channel Source Description
DTC
Activation
Priority*
0
ERI
Interrupt due to receive error (ORER, FER,
Not possible High
or PER)
RXI
Interrupt due to receive data full state (RDRF) Possible
TXI
Interrupt due to transmit data empty state
Possible
(TDRE)
TEI
Interrupt due to transmission end (TEND)
Not possible
1
ERI
Interrupt due to receive error (ORER, FER,
Not possible
or PER)
RXI
Interrupt due to receive data full state (RDRF) Possible
TXI
Interrupt due to transmit data empty state
Possible
(TDRE)
TEI
Interrupt due to transmission end (TEND)
Not possible Low
Note: * This table shows the initial state immediately after a reset. Relative priorities among
channels can be changed by means of ICR and IPR.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
TXI interrupt are requested simultaneously, the TXI interrupt may be accepted first, with the
result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted
in this case.
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