HD6432345 Datasheet, PDF (571/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

17.6.5 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 17.11.
In order for these registers to be accessed, the FLSHE bit must be set to 1 in SYSCR2.
Table 17.11 Flash Memory Registers
Register Name
Abbreviation R/W
Initial Value Address*¹
Flash memory control register 1
FLMCR1*⁶
R/W*³ H'00*⁴
H'FFC8*²
Flash memory control register 2
FLMCR2*⁶
R/W*³ H'00*⁵
H'FFC9*²
Erase block register 1
EBR1*⁶
R/W*³ H'00*⁵
H'FFCA*²
Erase block register 2
EBR2*⁶
R/W*³ H'00*⁵
H'FFCB*²
System control register 2
SYSCR2
R/W
H'00
H'FF42
RAM emulation register
RAMER
R/W
H'00
H'FEDB
Notes: 1. Lower 16 bits of the address.
2. Flash memory registers share addresses with other registers. Register selection is
performed by the FLSHE bit in the system control register 2 (SYSCR2).
3. In modes in which the on-chip flash memory is disabled (modes 4 and 5), a read will
return H'00, and writes are invalid. Writes are also disabled when the FWE bit is cleared
to 0 in FLMCR1.
4. When a high level is input to the FWE pin, the initial value is H'80.
5. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in
FLMCR1 is not set, these registers are initialized to H'00.
6. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid
for these registers, the access requiring 2 states.
The registers listed in table 7.11 are enabled on the F-ZTAT version only. They do not exist
on the ZTAT, mask ROM, and ROMless versions, so an undefined value will be returned if
they are read, and it is not possible to write to these registers.
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