HD6432345 Datasheet, PDF (634/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
If a transition is made to sleep mode when all modules are stopped (MSTPCR = H'FFFF), or
modules other than the 8-bit timers are stopped (MSTPCR = H'EFFF), operation of the bus
controller and I/O ports is also halted, enabling current dissipation to be further reduced.
Table 19.3 MSTP Bits and Corresponding On-Chip Supporting Modules
Register
Bit
Module
MSTPCRH MSTP15 —
MSTP14 Data transfer controller (DTC)
MSTP13 16-bit timer pulse unit (TPU)
MSTP12 8-bit timer
MSTP11 —
MSTP10 D/A converter
MSTP9 A/D converter
MSTP8 —
MSTPCRL MSTP7 —
MSTP6 Serial communication interface (SCI) channel 1
MSTP5 Serial communication interface (SCI) channel 0
MSTP4 —
MSTP3 —
MSTP2 —
MSTP1 —
MSTP0 —
Note: Bits 15, 11, 8, 7, and 4 to 0 can be read or written to, but do not affect operation.
19.5.2 Usage Notes
DTC Module Stop: Depending on the operating status of the DTC, the MSTP14 bit may not be
set to 1. Setting of the DTC module stop mode should be carried out only when the respective
module is not activated.
For details, refer to section 7, Data Transfer Controller (DTC).
On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in
module stop mode. Consequently, if module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or the DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
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