HD6432345 Datasheet, PDF (273/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

8.9.2 Register Configuration
Table 8.15 shows the port D register configuration.
Table 8.15 Port D Registers
Name
Abbreviation R/W
Port D data direction register
PDDDR
W
Port D data register
PDDR
R/W
Port D register
PORTD
R
Port D MOS pull-up control register PDPCR
R/W
Note: * Lower 16 bits of the address.
Initial Value
H'00
H'00
Undefined
H'00
Address *
H'FEBC
H'FF6C
H'FF5C
H'FF73
Port D Data Direction Register (PDDDR)
Bit
:
7
6
5
4
3
2
1
0
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value :
0
0
0
0
0
0
0
0
R/W
:
W
W
W
W
W
W
W
W
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be read..
PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode.
• Modes 1, 2, 4, 5, and 6*
The input/output direction specification by PDDDR is ignored, and port D is automatically
designated for data I/O.
• Modes 3 and 7*
Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing
the bit to 0 makes the pin an input port.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
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