HD6432345 Datasheet, PDF (383/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Contention between TGR Write and Input Capture: If the input capture signal is generated in
the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to
TGR is not performed.
Figure 9.54 shows the timing in this case.
ø
Address
Write signal
Input capture
signal
TCNT
TGR
TGR write cycle
T1
T2
TGR address
M
M
Figure 9.54 Contention between TGR Write and Input Capture
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