HD6432345 Datasheet, PDF (650/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Control Signal Timing: Table 20.5 lists the control signal timing.
Table 20.5 Control Signal Timing
Condition A: —In planning stage—
V_CC = AV_CC = 3.0 to 5.5 V, V_ref = 3.0 V to AV_CC, V_SS = AV_SS = 0 V,
ø = 2 to 10 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition B: V_CC = AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC, V_SS = AV_SS = 0 V,
ø = 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition A
Item
Symbol Min Max
RES setup time
t _RESS
RES pulse width
t _RESW
NMI reset setup time
t _NMIRS
NMI reset hold time
t _NMIRH
Mode programming setup time t_MDS
NMI setup time
t _NMIS
NMI hold time
t _NMIH
NMI pulse width (exiting
t _NMIW
software standby mode)
200 —
20 —
250 —
200 —
200 —
250 —
10 —
200 —
IRQ setup time
IRQ hold time
IRQ pulse width (exiting
software standby mode)
t _IRQS
t _IRQH
t _IRQW
250 —
10 —
200 —
Condition B
Min Max Unit
200 — ns
20
—
t _cyc
200 — ns
200 — ns
200 — ns
150 — ns
10 — ns
200 — ns
150 — ns
10 — ns
200 — ns
Test Conditions
Figure 20.9
Figure 20.10
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