HD6432345 Datasheet, PDF (723/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table A.2 Instruction Codes (cont)
Instruc-
tion
Mnemonic
XORC
XORC #xx:8,CCR
XORC #xx:8,EXR
Size
B
B
1st byte
05
01
2nd byte
IMM
41
3rd byte
05
4th byte
IMM
Instruction Format
5th byte 6th byte
7th byte
8th byte
9th byte 10th byte
Note: * Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0.
Legend
IMM:
abs:
disp:
rs, rd, rn:
ers, erd, ern, erm:
Immediate data (2, 3, 8, 16, or 32 bits)
Absolute address (8, 16, 24, or 32 bits)
Displacement (8, 16, or 32 bits)
Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.)
Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand
symbols ERs, ERd, ERn, and ERm.)
The register fields specify general registers as follows.
Address Register
32-Bit Register
16-Bit Register
Register
Field
General
Register
Register
Field
General
Register
000
ER0
001
ER1
•
•
•
•
•
•
111
ER7
0000
R0
0001
R1
•
•
•
•
•
•
0111
R7
1000
E0
1001
E1
•
•
•
•
•
•
1111
E7
8-Bit Register
Register
Field
General
Register
0000
0001
•
•
•
0111
1000
1001
•
•
•
1111
R0H
R1H
•
•
•
R7H
R0L
R1L
•
•
•
R7L