HD6432345 Datasheet, PDF (803/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

DTCERA to DTCERF—DTC Enable Registers H'FF30 to H'FF34
DTC
Bit
:
Initial value :
Read/Write :
7
DTCE7
0
R/W
6
DTCE6
0
R/W
5
DTCE5
0
R/W
4
DTCE4
0
R/W
3
DTCE3
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
0
DTCE0
0
R/W
DTC Activation Enable
DTC activation by this interrupt is disabled
0 [Clearing conditions]
• When the DISEL bit is 1 and data transfer has ended
•When the specified number of transfers have ended
DTC activation by this interrupt is enabled
1 ^{[Holding condition]}
When the DISEL bit is 0 and the specified number of
transfers have not ended
Correspondence between Interrupt Sources and DTCER
Register
DTCERA
DTCERB
DTCERC
DTCERD
DTCERE
7
IRQ0
—
TGI2A
—
—
6
IRQ1
ADI
TGI2B
—
—
5
IRQ2
TGI0A
TGI3A
TGI5A
—
Bits
4
IRQ3
TGI0B
TGI3B
TGI5B
—
3
IRQ4
TGI0C
TGI3C
CMIA0
RXI0
2
IRQ5
TGI0D
TGI3D
CMIB0
TXI0
1
IRQ6
TGI1A
TGI4A
CMIA1
RXI1
0
IRQ7
TGI1B
TGI4B
CMIB1
TXI1
794