HD6432345 Datasheet, PDF (378/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Contention between TCNT Write and Clear Operations: If the counter clear signal is
generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT
write is not performed.
Figure 9.49 shows the timing in this case.
TCNT write cycle
T1
T2
ø
Address
TCNT address
Write signal
Counter clear
signal
TCNT
N
H'0000
Figure 9.49 Contention between TCNT Write and Clear Operations
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