HD6432345 Datasheet, PDF (398/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

ø
External clock
input
Clock input
to TCNT
TCNT
N–1
N
N+1
Figure 10.3 Count Timing for External Clock Input
10.3.2 Compare Match Timing
Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in
TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match.
The compare match signal is generated at the last state in which the match is true, just before the
timer counter is updated.
Therefore, when TCOR and TCNT match, the compare match signal is not generated until the
next incrementation clock input. Figure 10.4 shows this timing.
ø
TCNT
N
N+1
TCOR
N
Compare match
signal
CMF
Figure 10.4 Timing of CMF Setting
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