HD6432345 Datasheet, PDF (551/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

17.2.2 Bus Control Register L (BCRL)
Bit
:
7
6
5
4
3
2
1
0
BRLE
—
EAE
—
—
—
—
WAITE
Initial value :
0
0
1
1
1
1
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enabling or disabling of part of the H8S/2345’s on-chip ROM area can be selected by means of
the EAE bit in BCRL. For details of the other bits in BCRL, see 6.2.5, Bus Control Register L.
Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are
to be internal addresses or external addresses.
Bit 5
EAE
Description
0
Addresses H'010000 to H'01FFFF are in on-chip ROM (H8S/2345).
Addresses H'010000 to H'017FFF are in on-chip ROM and addresses H'018000 to
H'01FFFF are a reserved area (in the H8S/2344).
Addresses H'010000 to H'01FFFF are a reserved area (in the H8S/2343 and
H8S/2341).
1
Addresses H'010000 to H'01FFFF are external addresses (external expansion mode)
or a reserved area* (single-chip mode).
(Initial value)
Note: * Reserved areas should not be accessed.
17.3 Operation
The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can
be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to
the lower 8 bits. Word data must start at an even address.
The on-chip ROM is enabled and disabled by setting the mode pins (MD₂, MD₁, and MD₀) and bit
EAE in BCRL. These settings are shown in tables 17.2 and 17.3.
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