HD6432345 Datasheet, PDF (863/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

TCR2—Timer Control Register 2
H'FFF0
TPU2
Bit
:
7
6
5
4
3
2
1
0
— CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value :
0
0
0
0
0
0
0
0
Read/Write : —
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Time Prescaler
0 0 0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
1 0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 External clock: counts on TCLKC pin input
1 Internal clock: counts on ø/1024
Note: This setting is ignored when channel 2 is in phase
counting mode.
Clock Edge
0 0 Count at rising edge
1 Count at falling edge
1 * Count at both edges
*: Don’t care
Note: This setting is ignored when channel 2
is in phase counting mode.
Counter Clear
0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1 _{TCNT cleared by counter clearing for another channel}
performing synchronous clearing/synchronous operation*
Note: * Synchronous operating setting is performed by setting
the SYNC bit TSYR to 1.
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