HD6432345 Datasheet, PDF (405/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

10.6.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T₂ state of a TCNT write cycle, the write
takes priority and the counter is not incremented.
Figure 10.11 shows this operation.
TCNT write cycle by CPU
T₁
T₂
ø
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 10.11 Contention between TCNT Write and Increment
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