HD6432345 Datasheet, PDF (590/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Start
Set SWE bit in FLMCR1
Wait (x) µs
*5
Store 32-byte program data in program _*4
data area and reprogram data area
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
n=1
m=0
Write 32-byte data in RAM reprogram data _*1
area consecutively to flash memory
Enable WDT
n←n+1
Set PSU bit in FLMCR2
Wait (y) µs
*5
Set P bit in FLMCR1
Wait (z) µs
Start of programming
*5
Increment address
Clear P bit in FLMCR1
Wait (α) µs
Clear PSU bit in FLMCR2
Wait (β) µs
Disable WDT
Set PV bit in FLMCR1
Wait (γ) µs
H'FF dummy write to verify address
Wait (ε) µs
Read verify data
*3
Program data =
verify data?
OK
Reprogram data computation
End of programming
Notes: 1. Data transfer is performed by byte transfer. The lower
*5
8 bits of the first address written to must be H'00, H'20, H'40,
H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer
must be performed even if writing fewer than 32 bytes;
in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
*5
3. Even bits for which programming has been completed in a 32-byte
programming loop will be subjected to additional programming if
the subsequent verify operation fails.
4. An area for storing program data (32 bytes) and reprogram data
(32 bytes) must be provided in RAM. The contents of the latter
are rewritten as programming progresses.
5. The values of x, y, z, α, β, γ, ε, η, and N are shown in section
*5
20.1.6, Flash Memory Characteristics.
Program Verify
Data
Data
Reprogram
Data
Comments
0
0
1
Programmed bits are
*5
not reprogrammed
0
1
0
Programming incomplete;
*2
reprogram
1
0
1
—
NG
m=1
*3
1
1
1
Still in erased state;
no action
Note: The memory erased state is 1. Programming is
performed on 0 reprogram data.
Transfer reprogram data to reprogram _*4
data area
NG
End of 32-byte
data verification?
OK
Clear PV bit in FLMCR1
RAM
Program data storage
area (32 bytes)
Wait (η) µs
m = 0?
OK
Clear SWE bit in FLMCR1
End of programming
*5
NG
*5
n ≥ N?
NG
OK
Clear SWE bit in FLMCR1
Programming failure
Reprogram data storage
area (32 bytes)
Figure 17.21 Program/Program-Verify Flowchart
578