HD6432345 Datasheet, PDF (795/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

ABWCR—Bus Width Control Register
H'FED0
Bus Controller
Bit
:
7
ABW7
Modes 1 to 3, 5 to 7
Initial value :
1
R/W
: R/W
Mode 4
Initial value :
0
Read/Write : R/W
6
5
ABW6 ABW5
1
1
R/W R/W
0
0
R/W R/W
4
3
2
ABW4 ABW3 ABW2
1
1
1
R/W R/W R/W
0
0
0
R/W R/W R/W
1
0
ABW1 ABW0
1
1
R/W R/W
0
0
R/W R/W
Area 7 to 0 Bus Width Control
0 Area n is designated for 16-bit access
1 Area n is designated for 8-bit access
(n = 7 to 0)
ASTCR—Access State Control Register
H'FED1
Bus Controller
Bit
:
Initial value :
Read/Write :
7
AST7
1
R/W
6
AST6
1
R/W
5
AST5
1
R/W
4
AST4
1
R/W
3
AST3
1
R/W
2
AST2
1
R/W
1
AST1
1
R/W
0
AST0
1
R/W
Area 7 to 0 Access State Control
0 Area n is designated for 2-state access
Wait state insertion in area n external space is disabled
1 Area n is designated for 3-state access
Wait state insertion in area n external space is enabled
(n = 7 to 0)
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